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| 1. general description the SC16C550B is a universal asynchronous receiver and transmitter (uart) used for serial data communications. its principal function is to convert parallel data into serial data, and vice versa. the uart can handle serial data rates up to 3 mbit/s. the SC16C550B is pin compatible with the st16c550, tl16c550 and pc16c550, and it will power-up to be functionally equivalent to the 16c450. the SC16C550B also provides dma mode data transfers through fifo trigger levels and the txrd y and rxrd y signals ( txrd y and rxrd y are not supported in the hvqfn32 package). on-board status registers provide the user with error indications, operational status, and modem interface control. system interrupts may be tailored to meet user requirements. an internal loopback capability allows on-board diagnostics. the SC16C550B operates at 5 v, 3.3 v and 2.5 v, and the industrial temperature range, and is available in plastic hvqfn32, dip40, plcc44 and lqfp48 packages. 2. features n 5 v, 3.3 v and 2.5 v operation n industrial temperature range n after reset, all registers are identical to the typical 16c450 register set n capable of running with all existing generic 16c450 software n pin compatibility with the industry-standard st16c450/550, tl16c450/550, pc16c450/550 n up to 3 mbit/s transmit/receive operation at 5 v, 2 mbit/s at 3.3 v, and 1 mbit/s at 2.5 v n 16 byte transmit fifo n 16 byte receive fifo with error ?ags n programmable auto- r ts and auto- cts u in auto- cts mode, cts controls transmitter u in auto- r ts mode, rx fifo contents and threshold control r ts n automatic hardware ?ow control n software selectable baud rate generator n four selectable receive fifo interrupt trigger levels n standard modem interface n standard asynchronous error and framing bits (start, stop, and parity overrun break) n independent receiver clock input n transmit, receive, line status, and data set interrupts independently controlled SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos rev. 04 16 march 2007 product data sheet
SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 2 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos n fully programmable character formatting: u 5, 6, 7, or 8-bit characters u even, odd, or no-parity formats u 1, 1 1 2 , or 2-stop bit u baud generation (up to 3 mbit/s) n false start-bit detection n complete status reporting capabilities n 3-state output ttl drive capabilities for bidirectional data bus and control bus n line break generation and detection n internal diagnostic capabilities: u loopback controls for communications link fault isolation n prioritized interrupt system controls n modem control functions ( cts, ri, dcd, dsr, dtr, r ts) 3. ordering information table 1. ordering information industrial: v cc = 2.5 v, 3.3 v or 5 v 10 %; t amb = - 40 c to +85 c. type number package name description version SC16C550Bia44 plcc44 plastic leaded chip carrier; 44 leads sot187-2 SC16C550Bibs hvqfn32 plastic thermal enhanced very thin quad ?at package; no leads; 32 terminals; body 5 5 0.85 mm sot617-1 SC16C550Bib48 lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2 SC16C550Bin40 dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 3 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 4. block diagram fig 1. block diagram of SC16C550B dtr rts out1, out2 transmit fifo registers tx receive shift register receive fifo registers rx interconnect bus lines and control signals SC16C550B transmit shift register xtal2 baudout xtal1 rclk 002aaa585 ddis data b u s and control logic register select logic interrupt control logic d0 to d7 ior, ior iow, iow reset a0 to a2 cs0, cs1, cs2 as int txrdy rxrdy clock and baud rate generator modem control logic cts ri dcd dsr SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 4 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 5. pinning information 5.1 pinning fig 2. pin con?guration for plcc44 fig 3. pin con?guration for hvqfn32 SC16C550Bia44 d5 reset d6 out1 d7 dtr rclk rts rx out2 n.c. n.c. tx int cs0 rxrdy cs1 a0 cs2 a1 baudout a2 xtal1 d4 xtal2 d3 iow d2 iow d1 v ss d0 n.c. n.c. ior v cc ior ri ddis dcd txrdy dsr as cts 002aaa582 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 002aab556 SC16C550Bibs transparent top view a2 tx cs a1 rx a0 d7 int d6 rts d5 dtr n.c. reset d4 cts v ss xtal1 xtal2 iow v ss ior n.c. n.c. d3 d2 d1 d0 v cc ri dcd dsr 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 5 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos fig 4. pin con?guration for lqfp48 fig 5. pin con?guration for dip40 xtal1 xtal2 iow iow v ss ior ior ddis txrdy as reset out1 dtr rts out2 n.c. int rxrdy a0 a1 a2 ri dcd dsr cts d4 d3 d2 d1 d0 v cc d5 d6 d7 rclk n.c. rx tx cs0 cs1 cs2 baudout SC16C550Bib48 n.c. n.c. n.c. n.c. n.c. 002aaa583 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24 n.c. SC16C550Bin40 d0 v cc d1 ri d2 dcd d3 dsr d4 cts d5 reset d6 out1 d7 dtr rclk rts rx out2 tx int cs0 rxrdy cs1 a0 cs2 a1 baudout a2 xtal1 as xtal2 txrdy iow ddis iow ior v ss ior 002aaa584 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 21 24 23 26 25 40 39 38 37 36 35 34 33 32 31 30 29 28 27 SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 6 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 5.2 pin description table 2. pin description symbol pin type description plcc44 lqfp48 dip40 hvqfn32 a0 31 28 28 19 i register select. a2 to a0 are used during read and write operations to select the uart register to read from or write to. refer to t ab le 3 for register addresses and refer to as description. a1 30 27 27 18 a2 29 26 26 17 as 28 24 25 - i address strobe. when as is active (low), a0, a1, and a2 and cs0, cs1, and cs2 drive the internal select logic directly; when as is high, the register select and chip select signals are held at the logic levels they were in when the low-to-high transition of as occurred. ba udout 17 12 15 - o baud out. ba udout is a 16 clock signal for the transmitter section of the uart. the clock rate is established by the reference oscillator frequency divided by a divisor speci?ed in the baud generator divisor latches. ba udout may also be used for the receiver section by tying this output to rclk. in hvqfn32 package ba udout and rclk are bonded internally. cs0 [2] 14 9 12 - i chip select. when cs0 and cs1 are high and cs2 is low, these three inputs select the uart. when any of these inputs are inactive, the uart remains inactive (refer to as description). cs1 [2] 15 10 13 - cs2 [2] 16 11 14 - cs [2] ---8 cts [2] 40 38 36 24 i clear to send. cts is a modem status signal. its condition can be checked by reading bit 4 ( cts) of the modem status register. bit 0 ( cts) of the modem status register indicates that cts has changed states since the last read from the modem status register. if the modem status interrupt is enabled when cts changes levels and the auto- cts mode is not enabled, an interrupt is generated. this pin has no effect on the uarts transmit or receive operation. d7 to d0 9, 8, 7, 6, 5, 4, 3, 2 4, 3, 2, 47, 46, 45, 44, 43 8, 7, 6, 5, 4, 3, 2, 1 5, 4, 3, 1, 32, 31, 30, 29 i/o data bus. eight data lines with 3-state outputs provide a bidirectional path for data, control and status information between the uart and the cpu. dcd [2] 42 40 38 26 i data carrier detect. dcd is a modem status signal. its condition can be checked by reading bit 7 ( dcd) of the modem status register. bit 3 ( dcd) of the modem status register indicates that dcd has changed states since the last read from the modem status register. if the modem status interrupt is enabled when dcd changes levels, an interrupt is generated. ddis 26 22 23 - o driver disable. ddis is active (low) when the cpu is not reading data. when active, ddis can disable an external transceiver. SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 7 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos dsr [2] 41 39 37 25 i data set ready. dsr is a modem status signal. its condition can be checked by reading bit 5 ( dsr) of the modem status register. bit 1 ( dsr) of the modem status register indicates dsr has changed levels since the last read from the modem status register. if the modem status interrupt is enabled when dsr changes levels, an interrupt is generated. dtr 37 33 33 22 o data terminal ready. when active (low), dtr informs a modem or data set that the uart is ready to establish communication. dtr is placed in the active level by setting the dtr bit of the modem control register. dtr is placed in the inactive level either as a result of a master reset, during loopback mode operation, or clearing the dtr bit. int 33 30 30 20 o interrupt. when active (high), int informs the cpu that the uart has an interrupt to be serviced. four conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (fifo mode only), an empty transmitter holding register or an enabled modem status interrupt. int is reset (deactivated) either when the interrupt is serviced or as a result of a master reset. n.c. 1, 12, 23, 34 1, 6, 13, 21, 25, 36, 37, 48 - 2, 15, 16 - not connected out1 38 34 34 - o outputs 1 and 2. these are user-designated output terminals that are set to the active (low) level by setting respective modem control register (mcr) bits ( out1 and out2). out1 and out2 are set to inactive the (high) level as a result of master reset, during loopback mode operations, or by clearing bit 2 ( out1) or bit 3 ( out2) of the mcr. out2 35 31 31 - rclk 10 5 9 - i receiver clock. rclk is the 16 baud rate clock for the receiver section of the uart. in the hvqfn32 package, ba udout and rclk are bonded internally. ior 25 20 22 - i read inputs. when either ior or ior is active (low or high, respectively) while the uart is selected, the cpu is allowed to read status information or data from a selected uart register. only one of these inputs is required for the transfer of data during a read operation; the other input should be tied to its inactive level (that is, ior tied low or ior tied high). ior [2] 24 19 21 14 reset 39 35 35 23 i master reset. when active (high), reset clears most uart registers and sets the levels of various output signals. table 2. pin description continued symbol pin type description plcc44 lqfp48 dip40 hvqfn32 SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 8 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos ri [2] 43 41 39 27 i ring indicator. ri is a modem status signal. its condition can be checked by reading bit 6 ( ri) of the modem status register. bit 2 ( d ri) of the modem status register indicates that ri has changed from a low to a high level since the last read from the modem status register. if the modem status interrupt is enabled when this transition occurs, an interrupt is generated. r ts 36 32 32 21 o request to send. when active, r ts informs the modem or data set that the uart is ready to receive data. r ts is set to the active level by setting the r ts modem control register bit and is set to the inactive (high) level either as a result of a master reset or during loopback mode operations or by clearing bit 1 ( r ts) of the mcr. this pin has no effect on the uarts transmit or receive operation. rxrd y322929- o receiver ready. receiver direct memory access (dma) signaling is available with rxrd y. when operating in the fifo mode, one of two types of dma signaling can be selected using the fifo control register bit 3 (fcr[3]). when operating in the 16c450 mode, only dma mode 0 is allowed. mode 0 supports single-transfer dma in which a transfer is made between cpu bus cycles. mode 1 supports multi-transfer dma in which multiple transfers are made continuously until the receiver fifo has been emptied. in dma mode 0 (fcr0 = 0 or fcr0 = 1, fcr3 = 0), when there is at least one character in the receiver fifo or receiver holding register, rxrd y is active (low). when rxrd y has been active but there are no characters in the fifo or holding register, rxrd y goes inactive (high). in dma mode 1 (fcr0 = 1, fcr3 = 1), when the trigger level or the time-out has been reached, rxrd y goes active (low); when it has been active but there are no more characters in the fifo or holding register, it goes inactive (high). this function does not exist in the hvqfn32 package. rx 11 7 10 6 i serial data input. rx is serial data input from a connected communications device. tx 13 8 11 7 o serial data output. tx is composite serial data output to a connected communication device. tx is set to the marking (high) level as a result of master reset. txrd y272324- o transmitter ready. transmitter dma signaling is available with txrd y. when operating in the fifo mode, one of two types of dma signaling can be selected using fcr[3]. when operating in the 16c450 mode, only dma mode 0 is allowed. mode 0 supports single-transfer dma in which a transfer is made between cpu bus cycles. mode 1 supports multi-transfer dma in which multiple transfers are made continuously until the transmit fifo has been ?lled. this function does not exist in the hvqfn32 package. v cc 44 42 40 28 power 2.5 v, 3.3 v or 5 v supply voltage. v ss 22 18 20 9, 13 [1] power ground voltage. table 2. pin description continued symbol pin type description plcc44 lqfp48 dip40 hvqfn32 SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 9 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos [1] hvqfn package die supply ground is connected to both the v ss pin and the exposed center pad. the v ss pin must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the printed-circuit board (pcb) in the thermal pad region. [2] this pin has a pull-up resistor. [3] in sleep mode, xtal2 is left ?oating. 6. functional description the SC16C550B provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. these functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol). data integrity is insured by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the SC16C550B is fabricated with an advanced cmos process to achieve low drain power and high speed requirements. the SC16C550B is an upward solution that provides 16 bytes of transmit and receive fifo memory, instead of none in the 16c450. the SC16C550B is designed to work with high speed modems and shared network environments that require fast data processing time. increased performance is realized in the SC16C550B by the larger transmit and receive fifos. this allows the external processor to handle more networking tasks within a given time. in addition, the four selectable levels of fifo trigger interrupt are provided for maximum data throughput performance, especially when operating in a multi-channel environment. the combination of the above greatly reduces the bandwidth requirement of the external controlling cpu, increases performance, and reduces power consumption. the SC16C550B is capable of operation up to 3 mbit/s with a 48 mhz external clock input (at 5 v). iow 211719- i write inputs. when either io w or iow is active (low or high, respectively) and while the uart is selected, the cpu is allowed to write control words or data into a selected uart register. only one of these inputs is required to transfer data during a write operation; the other input should be tied to its inactive level (that is, iow tied low or io w tied high). io w [2] 20 16 18 12 xtal1 18 14 16 10 i crystal connection or external clock input. xtal2 [3] 19 15 17 11 o crystal connection or the inversion of xtal1 if xtal1 is driven. table 2. pin description continued symbol pin type description plcc44 lqfp48 dip40 hvqfn32 SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 10 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 6.1 internal registers the SC16C550B provides 12 internal registers for monitoring and control. these registers are shown in t ab le 3 . these registers function as data holding registers (thr/rhr), interrupt status and control registers (ier/isr), a fifo control register (fcr), line status and control registers (lcr/lsr), modem status and control registers (mcr/msr), programmable data rate (clock) control registers (dll/dlm), and a user accessible scratchpad register (spr). register functions are more fully described in the following paragraphs. [1] these registers are accessible only when lcr[7] is a logic 0. [2] these registers are accessible only when lcr[7] is a logic 1. 6.2 fifo operation the 16-byte transmit and receive data fifos are enabled by the fifo control register bit-0 (fcr[0]). with 16c550 devices, the user can set the receive trigger level, but not the transmit trigger level. the receiver fifo section includes a time-out function to ensure data is delivered to the external cpu. an interrupt is generated whenever the receive holding register (rhr) has not been read following the loading of a character or the receive trigger level has not been reached. table 3. internal registers decoding a2 a1 a0 read mode write mode general register set (thr/rhr, ier/isr, mcr/msr, fcr/lsr, spr) [1] 0 0 0 receive holding register transmit holding register 0 0 1 interrupt enable register interrupt enable register 0 1 0 interrupt status register fifo control register 0 1 1 line control register line control register 1 0 0 modem control register modem control register 1 0 1 line status register n/a 1 1 0 modem status register n/a 1 1 1 scratchpad register scratchpad register baud rate register set (dll/dlm) [2] 0 0 0 lsb of divisor latch lsb of divisor latch 0 0 1 msb of divisor latch msb of divisor latch table 4. flow control mechanism selected trigger level (characters) int pin activation negate r ts assert r ts 1110 4440 8880 14 14 14 0 SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 11 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 6.3 auto?ow control auto?ow control is comprised of auto- cts and auto- r ts (see figure 6 ). with auto- cts, the cts input must be active before the transmitter fifo can emit data. with auto- r ts, r ts becomes active when the receiver needs more data and noti?es the sending serial device. when r ts is connected to cts, data transmission does not occur unless the receiver fifo has space for the data; thus, overrun errors are eliminated using uart 1 and uart 2 from a SC16C550B with the auto?ow control enabled. if not, overrun errors occur when the transmit data rate exceeds the receiver fifo read latency. 6.3.1 auto- r ts auto- r ts data ?ow control originates in the receiver timing and control block (refer to figure 1 bloc k diag r am of SC16C550B ) and is linked to the programmed receiver fifo trigger level (see figure 6 ). when the receiver fifo level reaches a trigger level of 1, 4, or 8 (see figure 8 ), r ts is de-asserted. with trigger levels of 1, 4, and 8, the sending uart may send an additional byte after the trigger level is reached (assuming the sending uart has another byte to send) because it may not recognize the de-assertion of r ts until after it has begun sending the additional byte. r ts is automatically reasserted once the rx fifo is emptied by reading the receiver buffer register. when the trigger level is 14 (see figure 9 ), r ts is de-asserted after the ?rst data bit of the 16th character is present on the rx line. r ts is reasserted when the rx fifo has at least one available byte space. 6.3.2 auto- cts the transmitter circuitry checks cts before sending the next data byte (see figure 6 ). when cts is active, it sends the next byte. to stop the transmitter from sending the following byte, cts must be released before the middle of the last stop bit that is currently being sent (see figure 7 ). the auto- cts function reduces interrupts to the host system. when ?ow control is enabled, cts level changes do not trigger host interrupts because the device automatically controls its own transmitter. without auto- cts, the transmitter sends any data present in the transmit fifo and a receiver overrun error may result. fig 6. auto?ow control (auto- r ts and auto- cts) example rcv fifo serial to parallel flow control xmt fifo parallel to serial flow control parallel to serial flow control serial to parallel flow xmt fifo rcv fifo ace1 ace2 d7 to d0 rx tx rts cts tx rx d7 to d0 control 002aaa048 cts rts SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 12 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 6.3.3 enabling auto?ow control and auto- cts auto?ow control is enabled by setting mcr[5] and mcr[1]. 6.3.4 auto- cts and auto- r ts functional timing the receiver fifo trigger level can be set to 1, 4, 8, or 14 bytes. these are described in figure 8 and figure 9 . table 5. enabling auto?ow control and auto- cts mcr[5] mcr[1] selection 1 1 auto r ts and cts 1 0 auto cts 0 x disable (1) when cts is low, the transmitter keeps sending serial data out. (2) if cts goes high before the middle of the last stop bit of the current byte, the transmitter ?nishes sending the current byte, but it does not send the next byte. (3) when cts goes from high to low, the transmitter begins sending data again. fig 7. cts functional timing waveforms start bits 0 to 7 stop tx cts 002aaa049 start bits 0 to 7 stop start bits 0 to 7 stop (1) n = rcv fifo trigger level (1, 4, or 8 bytes). (2) the two blocks in dashed lines cover the case where an additional byte is sent as described in section 6.3.1 . fig 8. r ts functional timing waveforms, rcv fifo trigger level = 1, 4, or 8 bytes start byte n start byte n + 1 start byte stop stop stop rx rts ior (rd rbr) n n + 1 12 002aaa050 SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 13 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 6.4 hardware/software and time-out interrupts following a reset, the transmitter interrupt is enabled, the SC16C550B will issue an interrupt to indicate that the transmit holding register is empty. this interrupt must be serviced prior to continuing operations. the isr register provides the current singular highest priority interrupt only. only after servicing the higher pending interrupt will the lower priority be re?ected in the status register. servicing the interrupt without investigating further interrupt conditions can result in data errors. when two interrupt conditions have the same priority, it is important to service these interrupts correctly. receive data ready and receive time-out have the same interrupt priority (when enabled by ier[0]). the receiver issues an interrupt after the number of characters have reached the programmed trigger level. in this case, the SC16C550B fifo may hold more characters than the programmed trigger level. following the removal of a data byte, the user should re-check lsr[0] for additional characters. a receive time-out will not occur if the receive fifo is empty. the time-out counter is reset at the center of each stop bit received or each time the receive holding register (rhr) is read. the actual time-out value is 4 character time, including data information length, start bit, parity bit, and the size of stop bit, that is, 1 , 1.5 , or 2 bit times. (1) r ts is de-asserted when the receiver receives the ?rst data bit of the sixteenth byte. the receive fifo is full after ?nishing the sixteenth byte. (2) r ts is asserted again when there is at least one byte of space available and no incoming byte is in processing, or there is more than one byte of space available. (3) when the receive fifo is full, the ?rst receive buffer register read re-asserts r ts. fig 9. r ts functional timing waveforms, rcv fifo trigger level = 14 bytes byte 14 byte 15 rx rts ior (rd rbr) start byte 18 stop start byte 16 stop 002aaa051 rts released after the first data bit of byte 16 SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 14 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 6.5 programmable baud rate generator the SC16C550B supports high speed modem technologies that have increased input data rates by employing data compression schemes. for example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. a 128.0 kbit/s isdn modem that supports data compression may need an input data rate of 460.8 kbit/s. the SC16C550B can support a standard data rate of 921.6 kbit/s. a single baud rate generator is provided for the transmitter and receiver, allowing independent tx/rx channel control. the programmable baud rate generator is capable of accepting an input clock up to 48 mhz, as required for supporting a 3 mbit/s data rate. the SC16C550B can be con?gured for internal or external clock operation. for internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the xtal1 and xtal2 pins (see figure 10 ). alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates (see t ab le 6 ). the generator divides the input 16 clock by any divisor from 1 to (2 16 - 1). the SC16C550B divides the basic crystal or external clock by 16. the frequency of the ba udout output pin is exactly 16 (16 times) of the selected baud rate (baudout = 16 baud rate). customized baud rates can be achieved by selecting the proper divisor values for the msb and lsb sections of the baud rate generator. programming the baud rate generator registers dlm (msb) and dll (lsb) provides a user capability for selecting the desired ?nal baud rate. the examples in t ab le 6 shows selectable baud rates when using a 1.8432 mhz crystal. for custom baud rates, the divisor value can be calculated using the following equation: (1) fig 10. crystal oscillator connection 002aaa870 c2 47 pf xtal1 xtal2 x1 1.8432 mhz c1 22 pf c2 33 pf xtal1 xtal2 1.5 k w x1 1.8432 mhz c1 22 pf divisor in decimal () xtal1 clock frequency serial data rate 16 ---------------------------------------------------------------- = SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 15 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 6.6 dma operation the SC16C550B fifo trigger level provides additional ?exibility to the user for block mode operation. the user can optionally operate the transmit and receive fifos in the dma mode (fcr[3]). the dma mode affects the state of the rxrd y and txrd y output pins. t ab le 7 and t ab le 8 show this. remark: dma operation is not supported in the hvqfn32 package. table 6. baud rates using 1.8432 mhz or 3.072 mhz crystal using 1.8432 mhz crystal using 3.072 mhz crystal desired baud rate divisor for 16 clock baud rate error desired baud rate divisor for 16 clock baud rate error 50 2304 50 3840 75 1536 75 2560 110 1047 0.026 110 1745 0.026 134.5 857 0.058 134.5 1428 0.034 150 768 150 1280 300 384 300 640 600 192 600 320 1200 96 1200 160 1800 64 1800 107 0.312 2000 58 0.69 2000 96 2400 48 2400 80 3600 32 3600 53 0.628 4800 24 4800 40 7200 16 7200 27 1.23 9600 12 9600 20 19200 6 19200 10 38400 3 38400 5 56000 2 2.86 table 7. effect of dma mode on state of rxrd y pin non-dma mode dma mode 1 = fifo empty 0-to-1 transition when fifo empties 0 = at least 1 byte in fifo 1-to-0 transition when fifo reaches trigger level, or time-out occurs table 8. effect of dma mode on state of txrd y pin non-dma mode dma mode 1 = at least 1 byte in fifo 1 = fifo is full 0 = fifo empty 0 = fifo is empty SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 16 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 6.7 loopback mode the internal loopback capability allows on-board diagnostics. in the loopback mode, the normal modem interface pins are disconnected and recon?gured for loopback internally. mcr[0:3] register bits are used for controlling loopback diagnostic testing. in the loopback mode, out1 and out2 in the mcr register (bits 3:2) control the modem ri and dcd inputs, respectively. mcr signals dtr and r ts (bits 0:1) are used to control the modem cts and dsr inputs, respectively. the transmitter output (tx) and the receiver input (rx) are disconnected from their associated interface pins, and instead are connected together internally (see figure 11 ). the inputs cts, dsr, dcd, and ri are disconnected from their normal modem control input pins, and instead are connected internally to dtr, r ts, out1 and out2. loopback test data is entered into the transmit holding register via the user data bus interface, d0 to d7. the transmit uart serializes the data and passes the serial data to the receive uart via the internal loopback connection. the receive uart converts the serial data back into parallel data that is then made available at the user data interface d0 to d7. the user optionally compares the received data to the initial transmitted data for verifying error-free operation of the uart tx/rx circuits. in this mode, the receiver and transmitter interrupts are fully operational. the modem control interrupts are also operational. however, the interrupts can only be read using the lower four bits of the modem status register (msr[0:3]) instead of the four modem status register bits 4:7. the interrupts are still controlled by the ier. SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 17 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos fig 11. internal loopback mode diagram cts transmit fifo registers tx receive shift register receive fifo registers rx interconnect bus lines and control signals SC16C550B transmit shift register 002aaa587 data b u s and control logic register select logic interrupt control logic d0 to d7 ior, ior iow, iow reset int txrdy rxrdy clock and baud rate generator modem control logic rts dsr dtr ri out1 dcd out2 mcr[4] = 1 xtal2 baudout xtal1 rclk ddis a0 to a2 cs0, cs1, cs2 as SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 18 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 7. register descriptions t ab le 9 details the assigned bit functions for the ?fteen SC16C550B internal registers. the assigned bit functions are more fully de?ned in section 7.1 through section 7.10 . [1] the value shown represents the registers initialized hex value; x = not applicable. [2] these registers are accessible only when lcr[7] is set to a logic 0. [3] these functions are not supported in the hvqfn32 package, and should not be written. [4] out2 pin is not supported in the hvqfn32 package. [5] the special register set is accessible only when lcr[7] is set to a logic 1. table 9. SC16C550B internal registers a2 a1 a0 register default [1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 general register set [2] 0 0 0 rhr xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 thr xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 ier 00 modem status interrupt receive line status interrupt transmit holding register receive holding register 0 1 0 fcr 00 rcvr trigger (msb) rcvr trigger (lsb) reserved reserved dma mode select [3] xmit fifo reset rcvr fifo reset fifo enable 0 1 0 isr 01 fifos enabled fifos enabled 0 0 int priority bit 2 int priority bit 1 int priority bit 0 int status 0 1 1 lcr 00 divisor latch enable set break set parity even parity parity enable stop bits word length bit 1 word length bit 0 1 0 0 mcr 00 reserved auto ?ow control enable loopback out2 [4] , int enable out1 [3] r ts dtr 1 0 1 lsr 60 fifo data error transmit empty transmit holding empty break interrupt framing error parity error overrun error receive data ready 1 1 0 msr x0 dcd ri dsr cts d dcd d ri d dsr d cts 1 1 1 spr ff bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 special register set [5] 0 0 0 dll xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 dlm xx bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 19 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 7.1 transmit (thr) and receive (rhr) holding registers the serial transmitter section consists of an 8-bit transmit hold register (thr) and transmit shift register (tsr). the status of the thr is provided in the line status register (lsr). writing to the thr transfers the contents of the data bus (d[7:0]) to the thr, providing that the thr or tsr is empty. the thr empty ?ag in the lsr register will be set to a logic 1 when the transmitter is empty or when data is transferred to the tsr. note that a write operation can be performed when the thr empty ?ag is set (logi c 0 = fifo full; logi c 1 = at least one fifo location available). the serial receive section also contains an 8-bit receive holding register (rhr). receive data is removed from the SC16C550B and receive fifo by reading the rhr register. the receive section provides a mechanism to prevent false starts. on the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate. after 7 1 2 clocks, the start bit time should be shifted to the center of the start bit. at this time the start bit is sampled, and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. receiver status codes will be posted in the lsr. 7.2 interrupt enable register (ier) the interrupt enable register (ier) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. these interrupts would normally be seen on the int output pin. table 10. interrupt enable register bits description bit symbol description 7:4 ier[7:4] not used 3 ier[3] modem status interrupt. logic 0 = disable the modem status register interrupt (normal default condition) logic 1 = enable the modem status register interrupt 2 ier[2] receive line status interrupt. this interrupt will be issued whenever a fully assembled receive character is transferred from rsr to the rhr/fifo, that is, data ready, lsr[0]. logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt 1 ier[1] transmit holding register interrupt. this interrupt will be issued whenever the thr is empty, and is associated with lsr[1]. logic 0 = disable the transmitter empty interrupt (normal default condition) logic 1 = enable the transmitter empty interrupt 0 ier[0] receive holding register interrupt. this interrupt will be issued when the fifo has reached the programmed trigger level, or is cleared when the fifo drops below the trigger level in the fifo mode of operation. logic 0 = disable the receiver ready interrupt (normal default condition) logic 1 = enable the receiver ready interrupt SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 20 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 7.2.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr[0] = logic 1), and receive interrupts (ier[0] = logic 1) are enabled, the receive interrupts and register status will re?ect the following: ? the receive data available interrupts are issued to the external cpu when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. ? fifo status will also be re?ected in the user accessible isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared when the fifo drops below the trigger level. ? the data ready bit (lsr[0]) is set as soon as a character is transferred from the shift register to the receive fifo. it is reset when the fifo is empty. 7.2.2 ier versus receive/transmit fifo polled mode operation when fcr[0] = logic 1, resetting ier[0:3] enables the SC16C550B in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ? lsr[0] will be a logic 1 as long as there is one byte in the receive fifo. ? lsr[1:4] will provide the type of errors encountered, if any. ? lsr[5] will indicate when the transmit fifo is empty. ? lsr[6] will indicate when both the transmit fifo and transmit shift register are empty. ? lsr[7] will indicate any fifo data errors. 7.3 fifo control register (fcr) this register is used to enable the fifos, clear the fifos, set the receive fifo trigger levels, and select the dma mode. 7.3.1 dma mode (dma mode does not exist in the hvqfn32 package; see t ab le 9 .) 7.3.1.1 mode 0 (fcr bit 3 = 0) set and enable the interrupt for each single transmit or receive operation, and is similar to the 16c450 mode. transmit ready ( txrd y) will go to a logic 0 whenever an empty transmit space is available in the transmit holding register (thr). receive ready ( rxrd y) will go to a logic 0 whenever the receive holding register (rhr) is loaded with a character. 7.3.1.2 mode 1 (fcr bit 3 = 1) set and enable the interrupt in a block mode operation. the transmit interrupt is set when the transmit fifo is empty. the receive interrupt is set when the receive fifo ?lls to the programmed trigger level. however, the fifo continues to ?ll regardless of the programmed level until the fifo is full. rxrd y remains a logic 0 as long as the fifo ?ll level is above the programmed trigger level. SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 21 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 7.3.2 fifo mode table 11. fifo control register bits description bit symbol description 7:6 fcr[7] (msb), fcr[6] (lsb) rcvr trigger. these bits are used to set the trigger level for the receive fifo interrupt. an interrupt is generated when the number of characters in the fifo equals the programmed trigger level. however, the fifo will continue to be loaded until it is full. refer to t ab le 12 . 5:4 fcr[5] (msb), fcr[4] (lsb) not used; set to 00 3 fcr[3] dma mode select. logic 0 = set dma mode 0 (normal default condition) logic 1 = set dma mode 1 transmit operation in mode 0: when the SC16C550B is in the 16c450 mode (fifos disabled; fcr[0] = logic 0) or in the fifo mode (fifos enabled; fcr[0] = logic 1; fcr[3] = logic 0), and when there are no characters in the transmit fifo or transmit holding register, the txrd y pin will be a logic 0. once active, the txrd y pin will go to a logic 1 after the ?rst character is loaded into the transmit holding register. receive operation in mode 0: when the SC16C550B is in 16c450 mode, or in the fifo mode (fcr[0] = logic 1; fcr[3] = logic 0) and there is at least one character in the receive fifo, the rxrd y pin will be a logic 0. once active, the rxrd y pin will go to a logic 1 when there are no more characters in the receiver. transmit operation in mode 1: when the SC16C550B is in fifo mode (fcr[0] = logic 1; fcr[3] = logic 1), the txrd y pin will be a logic 1 when the transmit fifo is completely full. it will be a logic 0 if the transmit fifo is completely empty. receive operation in mode 1: when the SC16C550B is in fifo mode (fcr[0] = logic 1; fcr[3] = logic 1) and the trigger level has been reached, or a receive time-out has occurred, the rxrd y pin will go to a logic 0. once activated, it will go to a logic 1 after there are no more characters in the fifo. 2 fcr[2] xmit fifo reset. logic 0 = no fifo transmit reset (normal default condition) logic 1 = clears the contents of the transmit fifo and resets the fifo counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. 1 fcr[1] rcvr fifo reset. logic 0 = no fifo receive reset (normal default condition) logic 1 = clears the contents of the receive fifo and resets the fifo counter logic (the receive shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. 0 fcr[0] fifo enable. logic 0 = disable the transmit and receive fifo (normal default condition) logic 1 = enable the transmit and receive fifo. this bit must be a 1 when other fcr bits are written to, or they will not be programmed. SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 22 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 7.4 interrupt status register (isr) the SC16C550B provides four levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with four interrupt status bits. performing a read cycle on the isr will provide the user with the highest pending interrupt level to be serviced. no other interrupts are acknowledged until the pending interrupt is serviced. whenever the interrupt status register is read, the interrupt status is cleared. however, it should be noted that only the current pending interrupt is cleared by the read. a lower level interrupt may be seen after re-reading the interrupt status bits. t ab le 13 interr upt source shows the data values (bits 3:0) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. table 12. rcvr trigger levels fcr[7] fcr[6] rx fifo trigger level (bytes) 001 014 108 1114 table 13. interrupt source priority level isr[3] isr[2] isr[1] isr[0] source of the interrupt 1 0 1 1 0 lsr (receiver line status register) 2 0 1 0 0 rxrdy (received data ready) 2 1 1 0 0 rxrdy (receive data time-out) 3 0 0 1 0 txrdy (transmitter holding register empty) 4 0 0 0 0 msr (modem status register) table 14. interrupt status register bits description bit symbol description 7:6 isr[7:6] fifos enabled. these bits are set to a logic 0 when the fifo is not being used. they are set to a logic 1 when the fifos are enabled. logic 0 or cleared = default condition 5:4 isr[5:4] not used 3:1 isr[3:1] int priority bits 2:0. these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see t ab le 13 ). logic 0 or cleared = default condition 0 isr[0] int status. logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine logic 1 = no interrupt pending (normal default condition) SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 23 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 7.5 line control register (lcr) the line control register is used to specify the asynchronous data communication format. the word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. table 15. line control register bits description bit symbol description 7 lcr[7] divisor latch enable. the internal baud rate counter latch and enhance feature mode enable. logic 0 = divisor latch disabled (normal default condition) logic 1 = divisor latch and enhanced feature register enabled 6 lcr[6] set break. when enabled, the break control bit causes a break condition to be transmitted (the tx output is forced to a logic 0 state). this condition exists until disabled by setting lcr[6] to a logic 0. logic 0 = no tx break condition (normal default condition) logic 1 = forces the transmitter output (tx) to a logic 0 for alerting the remote receiver to a line break condition 5 lcr[5] set parity. if the parity bit is enabled, lcr[5] selects the forced parity format. programs the parity conditions (see t ab le 16 ). logic 0 = parity is not forced (normal default condition) lcr[5] = logic 1 and lcr[4] = logic 0: parity bit is forced to a logical 1 for the transmit and receive data lcr[5] = logic 1 and lcr[4] = logic 1: parity bit is forced to a logical 0 for the transmit and receive data 4 lcr[4] even parity. if the parity bit is enabled with lcr[3] set to a logic 1, lcr[4] selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1s in the transmitted data. the receiver must be programmed to check the same format (normal default condition). logic 1 = even parity is generated by forcing an even number of logic 1s in the transmitted data. the receiver must be programmed to check the same format. 3 lcr[3] parity enable. parity or no parity can be selected via this bit. logic 0 = no parity (normal default condition) logic 1 = a parity bit is generated during the transmission, receiver checks the data and parity for transmission errors 2 lcr[2] stop bits. the length of stop bit is speci?ed by this bit in conjunction with the programmed word length (see t ab le 17 ). logic 0 or cleared = default condition 1:0 lcr[1:0] word length bits [1:0]. these two bits specify the word length to be transmitted or received (see t ab le 18 ). logic 0 or cleared = default condition SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 24 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos table 16. lcr[5] parity selection lcr[5] lcr[4] lcr[3] parity selection x x 0 no parity 0 0 1 odd parity 011even parity 101f orced parity 1 111f orced parity 0 table 17. lcr[2] stop bit length lcr[2] word length stop bit length (bit times) 0 5, 6, 7, 8 1 15 1 1 2 1 6, 7, 8 2 table 18. lcr[1:0] word length lcr[1] lcr[0] word length 005 016 107 118 SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 25 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 7.6 modem control register (mcr) this register controls the interface with the modem or a peripheral device. table 19. modem control register bits description bit symbol description 7 mcr[7] reserved; set to 0 6 mcr[6] reserved; set to 0 5 mcr[5] auto ?ow control enable. 4 mcr[4] loopback. enable the local loopback mode (diagnostics). in this mode the transmitter output ( tx) and the receiver input ( rx), cts, dsr, dcd, and ri are disconnected from the SC16C550B i/o pins. internally the modem data and control pins are connected into a loopback data con?guration (see figure 11 ). in this mode, the receiver and transmitter interrupts remain fully operational. the modem control interrupts are also operational, but the interrupts sources are switched to the lower four bits of the modem control. interrupts continue to be controlled by the ier register. logic 0 = disable loopback mode (normal default condition) logic 1 = enable local loopback mode (diagnostics) 3 mcr[3] out2, intx enable. used to control the modem dcd signal in the loopback mode. logic 0 = forces int output to the 3-state mode. in the loopback mode, sets out2 ( dcd) internally to a logic 1. logic 1 = forces the int output to the active mode. in the loopback mode, sets out2 ( dcd) internally to a logic 0. 2 mcr[2] out1. this bit is used in the loopback mode only. in the loopback mode, this bit is used to write the state of the modem ri interface signal via out1. 1 mcr[1] r ts logic 0 = force r ts output to a logic 1 (normal default condition) logic 1 = force r ts output to a logic 0 0 mcr[0] dtr logic 0 = force dtr output to a logic 1 (normal default condition) logic 1 = force dtr output to a logic 0 SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 26 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 7.7 line status register (lsr) this register provides the status of data transfers between the SC16C550B and the cpu. table 20. line status register bits description bit symbol description 7 lsr[7] fifo data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current fifo data. this bit is cleared when lsr register is read. 6 lsr[6] thr and tsr empty. this bit is the transmit empty indicator. this bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. it is reset to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode, this bit is set to 1 whenever the transmit fifo and transmit shift register are both empty. 5 lsr[5] thr empty. this bit is the transmit holding register empty indicator. this bit indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to cpu when the thr interrupt enable is set. the thr bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. the bit is reset to a logic 0 concurrently with the loading of the transmitter holding register by the cpu. in the fifo mode, this bit is set when the transmit fifo is empty; it is cleared when at least 1 byte is written to the transmit fifo. 4 lsr[4] break interrupt. logic 0 = no break condition (normal default condition) logic 1 = the receiver received a break signal (rx was a logic 0 for one character frame time). in the fifo mode, only one break character is loaded into the fifo. 3 lsr[3] framing error. logic 0 = no framing error (normal default condition) logic 1 = framing error. the receive character did not have a valid stop bit(s). in the fifo mode, this error is associated with the character at the top of the fifo. 2 lsr[2] parity error. logic 0 = no parity error (normal default condition) logic 1 = parity error. the receive character does not have correct parity information and is suspect. in the fifo mode, this error is associated with the character at the top of the fifo. 1 lsr[1] overrun error. logic 0 = no overrun error (normal default condition) logic 1 = overrun error. a data overrun error occurred in the receive shift register. this happens when additional data arrives while the fifo is full. in this case, the previous data in the shift register is overwritten. note that under this condition, the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. 0 lsr[0] receive data ready. logic 0 = no data in receive holding register or fifo (normal default condition) logi c 1 = data has been received and is saved in the receive holding register or fifo SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 27 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 7.8 modem status register (msr) this register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C550B is connected. four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a control input from the modem changes state. these bits are set to a logic 0 whenever the cpu reads this register. [1] whenever any msr bit 0:3 is set to logic 1, a modem status interrupt will be generated. table 21. modem status register bits description bit symbol description 7 msr[7] data carrier detect . dcd (active high, logical 1). normally this bit is the complement of the dcd input. in the loopback mode this bit is equivalent to the out2 bit in the mcr register. 6 msr[6] ring indicator . ri (active high, logical 1). normally this bit is the complement of the ri input. in the loopback mode this bit is equivalent to the out1 bit in the mcr register. 5 msr[5] data set ready . dsr (active high, logical 1). normally this bit is the complement of the dsr input. in loopback mode this bit is equivalent to the dtr bit in the mcr register. 4 msr[4] clear to send . cts. cts functions as hardware ?ow control signal input if it is enabled via mcr[5]. the transmit holding register ?ow control is enabled/disabled by msr[4]. flow control (when enabled) allows starting and stopping the transmissions based on the external modem cts signal. a logic 1 at the cts pin will stop SC16C550B transmissions as soon as current character has ?nished transmission. normally msr[4] is the complement of the cts input. however, in the loopback mode, this bit is equivalent to the rts bit in the mcr register. 3 msr[3] d dcd [1] logic 0 = no dcd change (normal default condition) logic 1 = the dcd input to the SC16C550B has changed state since the last time it was read. a modem status interrupt will be generated. 2 msr[2] d ri [1] logic 0 = no ri change (normal default condition). logic 1 = the ri input to the SC16C550B has changed from a logic 0 to a logic 1. a modem status interrupt will be generated. 1 msr[1] d dsr [1] logic 0 = no dsr change (normal default condition) logic 1 = the dsr input to the SC16C550B has changed state since the last time it was read. a modem status interrupt will be generated. 0 msr[0] d cts [1] logic 0 = no cts change (normal default condition) logic 1 = the cts input to the SC16C550B has changed state since the last time it was read. a modem status interrupt will be generated. SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 28 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 7.9 scratchpad register (spr) the SC16C550B provides a temporary data register to store 8 bits of user information. 7.10 SC16C550B external reset conditions 8. limiting values table 22. reset state for registers register reset state ier ier[7:0] = 0 isr isr[7:1] = 0; isr[0] = 1 lcr lcr[7:0] = 0 mcr mcr[7:0] = 0 lsr lsr[7] = 0; lsr[6:5] = 1; lsr[4:0] = 0 msr msr[7:4] = input signals; msr[3:0] = 0 fcr fcr[7:0] = 0 table 23. reset state for outputs output reset state tx high r ts high dtr high rxrd y high txrd ylow table 24. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage - 7 v v n voltage on any other pin v ss - 0.3 v cc + 0.3 v t amb ambient temperature operating in free air - 40 +85 c t stg storage temperature - 65 +150 c p tot /pack total power dissipation per package - 500 mw SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 29 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 9. static characteristics [1] except for xtal2, v ol = 1 v typically. [2] refer to t ab le 2 pin descr iption for a listing of pins having internal pull-up resistors. table 25. static characteristics t amb = - 40 c to +85 c; tolerance of v cc = 10 %, unless otherwise speci?ed. symbol parameter conditions v cc = 2.5 v v cc = 3.3 v v cc = 5.0 v unit min max min max min max v il(clk) clock low-level input voltage - 0.3 0.45 - 0.3 0.6 - 0.5 0.6 v v ih(clk) clock high-level input voltage 1.8 v cc 2.4 v cc 3.0 v cc v v il low-level input voltage - 0.3 0.65 - 0.3 0.8 - 0.5 0.8 v v ih high-level input voltage 1.6 - 2.0 - 2.2 v cc v v ol low-level output voltage on all outputs [1] i ol =5ma (data bus) -----0.4v i ol =4ma (other outputs) - - - 0.4 - - v i ol =2ma (data bus) - 0.4 - - - - v i ol = 1.6 ma (other outputs) - 0.4 - - - - v v oh high-level output voltage i oh = - 5ma (data bus) ----2.4-v i oh = - 1ma (other outputs) - - 2.0 - - - v i oh = - 800 m a (data bus) 1.85 - - - - - v i oh = - 400 m a (other outputs) 1.85 - - - - - v i lil low-level input leakage current - 10 - 10 - 10 m a i l(clk) clock leakage current - 30 - 30 - 30 m a i cc(av) average supply current f = 5 mhz - 3.5 - 4.5 - 4.5 ma c i input capacitance - 5 - 5 - 5 pf r pu(int) internal pull-up resistance [2] 500 - 500 - 500 - k w xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 30 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 10. dynamic characteristics table 26. dynamic characteristics t amb = - 40 c to +85 c; tolerance of v cc 10 %, unless otherwise speci?ed. symbol parameter conditions v cc = 2.5 v v cc = 3.3 v v cc = 5.0 v unit min max min max min max t w1 clock pulse duration 15 - 13 - 10 - ns t w2 clock pulse duration 15 - 13 - 10 - ns f xtal clock frequency [1] [2] - 16 - 32 - 48 mhz t 4w address strobe width 45 - 35 - 25 - ns t 5s address setup time 5 - 5 - 1 - ns t 5h address hold time 5 - 5 - 5 - ns t 6s chip select setup time to as 10 - 5 - 0 - ns t 6h address hold time 0 - 0 - 0 - ns t 6s' address setup time [3] 10 - 10 - 5 - ns t 6h chip select hold time 0 - 0 - 0 - ns t 7d ior delay from chip select 10 - 10 - 10 - ns t 7w ior strobe width 25 pf load 77 - 26 - 23 - ns t 7h chip select hold time from ior 0- 0- 0- ns t 7h' address hold time [3] 5- 5- 5- ns t 8d ior delay from address 10 - 10 - 10 - ns t 9d read cycle delay 25 pf load 20 - 20 - 20 - ns t 11d ior to ddis delay 25 pf load - 100 - 35 - 30 ns t 12d delay from ior to data 25 pf load - 77 - 26 - 23 ns t 12h data disable time 25 pf load - 15 - 15 - 15 ns t 13d io w delay from chip select 10 - 10 - 10 - ns t 13w io w strobe width 20 - 20 - 15 - ns t 13h chip select hold time from io w 0-0-0-ns t 14d io w delay from address 10 - 10 - 10 - ns t 15d write cycle delay 25 - 25 - 20 - ns t 16s data setup time 20 - 20 - 15 - ns t 16h data hold time 15 - 5 - 5 - ns t 17d delay from io w to output 25 pf load - 100 - 33 - 29 ns t 18d delay to set interrupt from modem input 25 pf load - 100 - 24 - 23 ns t 19d delay to reset interrupt from ior 25 pf load - 100 - 24 - 23 ns xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 31 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos [1] applies to external clock, crystal oscillator max 24 mhz. [2] maximum frequency = [3] applicable only when as is tied low. t 20d delay from stop to set interrupt - 1t rclk -1t rclk -1t rclk s t 21d delay from ior to reset interrupt 25 pf load - 100 - 29 - 28 ns t 22d delay from start to set interrupt - 100 - 45 - 40 ns t 23d delay from io w to transmit start 8t rclk 24t rclk 8t rclk 24t rclk 8t rclk 24t rclk s t 24d delay from io w to reset interrupt - 100 - 45 - 40 ns t 25d delay from stop to set rxrd y-1t rclk -1t rclk -1t rclk s t 26d delay from ior to reset rxrd y - 100 - 45 - 40 ns t 27d delay from io w to set txrd y - 100 - 45 - 40 ns t 28d delay from start to reset txrd y-8t rclk -8t rclk -8t rclk s t reset reset pulse width 100 - 40 - 40 - ns n baud rate divisor 1 2 16 - 11 2 16 - 11 2 16 - 1 table 26. dynamic characteristics continued t amb = - 40 c to +85 c; tolerance of v cc 10 %, unless otherwise speci?ed. symbol parameter conditions v cc = 2.5 v v cc = 3.3 v v cc = 5.0 v unit min max min max min max 1 t w3 ------- SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 32 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 10.1 timing diagrams fig 12. general read timing when using as signal 002aaa331 t 4w t 7d t 5s t 7w a0 to a2 cs2 cs1, cs0 d0 to d7 t 5h t 6h t 6s t 8d t 7h t 9d t 11d t 11h t 12d t 12h as valid valid address ior, ior active active data ddis fig 13. general write timing when using as signal 002aaa332 t 4w t 13d t 5s t 13w d0 to d7 t 5h t 6h t 6s t 14d t 13h t 15d t 16s t 16h a0 to a2 cs2 cs1, cs0 as iow, iow data active valid valid address SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 33 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos fig 14. general read timing when as is tied to v ss 002aaa333 t 6s' t 7h' t 7w t 9d t 12d t 12h a0 to a2 ior d0 to d7 t 7h' t 6s' t 7w t 12d t 12h valid address valid address active active active data cs fig 15. general write timing when as is tied to v ss 002aaa334 t 6s' t 7h' t 13w t 15d a0 to a2 iow d0 to d7 t 7h' t 6s' t 16s t 16h t 16s t 16h data active active active t 13w cs valid address valid address SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 34 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos fig 16. modem input/output timing t 17d iow rts dtr dcd cts dsr int ior ri t 19d 002aaa347 t 18d change of state change of state change of state change of state active active active active active active change of state t 18d t 18d active fig 17. external clock timing external clock 002aaa112 t w3 t w2 t w1 f xtal 1 t w3 ------- = SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 35 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos fig 18. receive timing d0 d1 d2 d3 d4 d5 d6 d7 active active 16 baud rate clock 002aaa113 rx int ior t 21d t 20d 5 data bits 6 data bits 7 data bits stop bit parity bit start bit data bits (0 to 7) next data start bit fig 19. receive ready timing in non-fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab063 next data start bit stop bit parity bit t 25d rx rxrdy ior active data ready start bit data bits (0 to 7) active t 26d SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 36 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos fig 20. receive ready timing in fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab064 first byte that reaches the trigger level stop bit parity bit t 25d rx rxrdy ior active data ready start bit data bits (0 to 7) active t 26d fig 21. transmit timing active transmitter ready active 16 baud rate clock 002aaa116 t 24d int iow active d0 d1 d2 d3 d4 d5 d6 d7 tx 5 data bits 6 data bits 7 data bits stop bit parity bit start bit data bits (0 to 7) next data start bit t 22d t 23d SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 37 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos fig 22. transmit ready timing in non-fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aaa580 start bit t 27d txrdy iow data bits (0 to 7) active d0 to d7 byte #1 t 28d transmitter not ready active transmitter ready parity bit stop bit next data start bit tx fig 23. transmit ready timing in fifo mode (dma mode 1) d0 d1 d2 d3 d4 d5 d6 d7 002aab061 stop bit parity bit t 27d tx iow d0 to d7 start bit data bits (0 to 7) byte #16 txrdy t 28d fifo full active 5 data bits 6 data bits 7 data bits SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 38 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 11. package outline fig 24. package outline sot187-2 (plcc44) unit a a 1 min. a 4 max. b p ey w v b references outline version european projection issue date iec jedec jeita mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 16.66 16.51 1.27 17.65 17.40 2.16 45 o 0.18 0.1 0.18 dimensions (mm dimensions are derived from the original inch dimensions) note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. sot187-2 d (1) e (1) 16.66 16.51 h d h e 17.65 17.40 z d (1) max. z e (1) max. 2.16 b 1 0.81 0.66 k 1.22 1.07 0.180 0.165 0.02 0.12 a 3 0.25 0.01 0.656 0.650 0.05 0.695 0.685 0.085 0.007 0.004 0.007 l p 1.44 1.02 0.057 0.040 0.656 0.650 0.695 0.685 e d e e 16.00 14.99 0.63 0.59 16.00 14.99 0.63 0.59 0.085 0.032 0.026 0.048 0.042 29 39 44 1 6 717 28 18 40 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 b k x y e e b d h e e e h v m b d z d a z e e v m a pin 1 index 112e10 ms-018 edr-7319 0 5 10 mm scale 99-12-27 01-11-14 inches plcc44: plastic leaded chip carrier; 44 leads sot187-2 d e SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 39 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos fig 25. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2 SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 40 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos fig 26. package outline sot129-1 (dip40) unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec jeita mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot129-1 99-12-27 03-02-13 a min. a max. b z max. w m e e 1 1.70 1.14 0.53 0.38 0.36 0.23 52.5 51.5 14.1 13.7 3.60 3.05 0.254 2.54 15.24 15.80 15.24 17.42 15.90 2.25 4.7 0.51 4 0.067 0.045 0.021 0.015 0.014 0.009 2.067 2.028 0.56 0.54 0.14 0.12 0.01 0.1 0.6 0.62 0.60 0.69 0.63 0.089 0.19 0.02 0.16 051g08 mo-015 sc-511-40 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 40 1 21 20 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. (1) (1) (1) dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1 SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 41 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos fig 27. package outline sot617-1 (hvqfn32) 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 5.1 4.9 d h 3.25 2.95 y 1 5.1 4.9 3.25 2.95 e 1 3.5 e 2 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot617-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot617-1 hvqfn32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 916 32 25 24 17 8 1 x d e c b a e 2 terminal 1 index area terminal 1 index area 01-08-08 02-10-18 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 42 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 12. soldering 12.1 introduction there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 12.2 through-hole mount packages 12.2.1 soldering by dipping or by solder wave typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the speci?ed maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 12.2.2 manual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 c and 400 c, contact may be up to 5 seconds. 12.3 surface mount packages 12.3.1 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 28 ) than a pbsn process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 27 and 28 SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 43 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 28 . for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 12.3.2 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. table 27. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 28. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 msl: moisture sensitivity level fig 28. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 44 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 12.3.3 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 12.4 package related soldering information table 29. suitability of ic packages for wave, re?ow and dipping soldering methods mounting package [1] soldering method wave re?ow [2] dipping through-hole mount cpga, hcpga suitable -- dbs, dip, hdip, rdbs, sdip, sil suitable [3] - suitable through-hole-surface mount pmfp [4] not suitable not suitable - SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 45 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your nxp semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vapori zation of the moisture in them (the so called popcorn effect). [3] for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [4] hot bar soldering or manual soldering is suitable for pmfp packages. [5] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [6] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot pene trate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposite d on the heatsink surface. [7] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [8] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [9] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [10] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil . however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropri ate soldering pro?le can be provided on request. 13. abbreviations surface mount bga, htsson..t [5] , lbga, lfbga, sqfp, ssop..t [5] , tfbga, vfbga, xson not suitable suitable - dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [6] suitable - plcc [7] , so, soj suitable suitable - lqfp, qfp, tqfp not recommended [7] [8] suitable - ssop, tssop, vso, vssop not recommended [9] suitable - cwqccn..l [10] , wqccn..l [10] not suitable not suitable - table 29. suitability of ic packages for wave, re?ow and dipping soldering methods continued mounting package [1] soldering method wave re?ow [2] dipping table 30. abbreviations acronym description cpu central processing unit dll divisor latch lsb dlm divisor latch msb dma direct memory access fifo first-in, first-out isdn integrated service digital network SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 46 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 14. revision history lsb least signi?cant bit msb most signi?cant bit ttl transistor-transistor logic table 30. abbreviations continued acronym description table 31. revision history document id release date data sheet status change notice supersedes SC16C550B_4 20070316 product data sheet - SC16C550B_3 modi?cations: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? figure 5 pin con? gur ation f or dip40 : changed signal name for pin 35 from mr to reset; changed signal name for pin 31 from out2 to out2 ? t ab le 2 pin descr iption : C added t ab le note 1 and its reference at pin v ss C signal out2 in plcc44: pin number changed from 32 to 35 (in figure 2 pin con? gur ation f or plcc44 it was shown correctly) ? t ab le 8 eff ect of dma mode on state of txrd y pin , under column dma mode: changed 0 = fifo has at least 1 empty location to 0 = fifo is empty ? section 7.3.1.2 mode 1 (fcr bit 3 = 1) ,2 nd sentence: changed ... when the transmit fifo has at least one empty location. to ... when the transmit fifo is empty. ? t ab le 11 fifo control register bits descr iption , description of bit 3, transmit operation in mode 1: changed last sentence from it will be a logic 0 if one or more fifo locations are empty. to it will be a logic 0 if the transmit fifo is completely empty. ? t ab le 24 limiting v alues : C changed parameter for v n from voltage at any pin to voltage on any other pin; changed min value from gnd - 0.3 v to v ss - 0.3 v C changed parameter for t amb from operating temperature to ambient temperature; changed conditions to operating in free air C changed symbol p tot(pack) to p tot /pack ? t ab le 25 static char acter istics : C changed symbol v il(ck) to v il(clk) C changed symbol v ih(ck) to v ih(clk) C symbol v ol : moved on all outputs from parameter to conditions column C changed symbol i cl to i l(clk) C changed symbol i cc to i cc(av) ? t ab le 26 dynamic char acter istics , symbol n: removed t rclk from values; removed s from unit column (n is a number) ? in titles of figure 14 and figure 15 , changed ... tied to gnd to ... tied to v ss SC16C550B_3 (9397 750 14986) 20050620 product data sheet - SC16C550B-02 SC16C550B-02 (9397 750 14446) 20041214 product data - SC16C550B-01 SC16C550B-01 (9397 750 11967) 20040326 product data - SC16C550B_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 march 2007 47 of 48 nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 15.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 15.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 16. contact information for additional information, please visit: http://www .nxp.com for sales of?ce addresses, send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation. nxp semiconductors SC16C550B 5 v, 3.3 v and 2.5 v uart with 16-byte fifos ? nxp b.v. 2007. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 16 march 2007 document identifier: SC16C550B_4 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 functional description . . . . . . . . . . . . . . . . . . . 9 6.1 internal registers. . . . . . . . . . . . . . . . . . . . . . . 10 6.2 fifo operation . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3 auto?ow control . . . . . . . . . . . . . . . . . . . . . . . 11 6.3.1 auto- r ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.3.2 auto- cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.3.3 enabling auto?ow control and auto- cts . . . . 12 6.3.4 auto- cts and auto- r ts functional timing . . . 12 6.4 hardware/software and time-out interrupts. . . 13 6.5 programmable baud rate generator . . . . . . . . 14 6.6 dma operation . . . . . . . . . . . . . . . . . . . . . . . . 15 6.7 loopback mode . . . . . . . . . . . . . . . . . . . . . . . 16 7 register descriptions . . . . . . . . . . . . . . . . . . . 18 7.1 transmit (thr) and receive (rhr) holding registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.2 interrupt enable register (ier) . . . . . . . . . . . 19 7.2.1 ier versus receive fifo interrupt mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2.2 ier versus receive/transmit fifo polled mode operation. . . . . . . . . . . . . . . . . . . . . . . . 20 7.3 fifo control register (fcr) . . . . . . . . . . . . . 20 7.3.1 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.3.1.1 mode 0 (fcr bit 3 = 0) . . . . . . . . . . . . . . . . . . 20 7.3.1.2 mode 1 (fcr bit 3 = 1) . . . . . . . . . . . . . . . . . . 20 7.3.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.4 interrupt status register (isr) . . . . . . . . . . . . 22 7.5 line control register (lcr) . . . . . . . . . . . . . . 23 7.6 modem control register (mcr) . . . . . . . . . . . 25 7.7 line status register (lsr) . . . . . . . . . . . . . . . 26 7.8 modem status register (msr). . . . . . . . . . . . 27 7.9 scratchpad register (spr) . . . . . . . . . . . . . . 28 7.10 SC16C550B external reset conditions . . . . . . 28 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28 9 static characteristics. . . . . . . . . . . . . . . . . . . . 29 10 dynamic characteristics . . . . . . . . . . . . . . . . . 30 10.1 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 32 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 38 12 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.2 through-hole mount packages . . . . . . . . . . . 42 12.2.1 soldering by dipping or by solder wave . . . . . 42 12.2.2 manual soldering . . . . . . . . . . . . . . . . . . . . . . 42 12.3 surface mount packages . . . . . . . . . . . . . . . . 42 12.3.1 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 42 12.3.2 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 43 12.3.3 manual soldering . . . . . . . . . . . . . . . . . . . . . . 44 12.4 package related soldering information . . . . . . 44 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 45 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 46 15 legal information . . . . . . . . . . . . . . . . . . . . . . 47 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 47 15.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 15.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 47 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16 contact information . . . . . . . . . . . . . . . . . . . . 47 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 |
Price & Availability of SC16C550B
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